1. Field of the Invention
The present invention relates to computers and, more particularly, to methods for handling novel instructions for the transfer of packed data to and from a multimedia extended register file.
2. Description of Related Art
Today many computers perform multimedia operations which involve processing high volumes of small integer data elements representing audio signals and video images. In order to process the data efficiently, multiple data elements are joined together as packed data sequences. The packed data sequences enable the transfer of up to sixty-four bits of integer data. In addition to the conventional thirty-two bit integer register file, a second extended integer register file is provided to take advantage of the packed data sequences. The second register file typically has extended registers providing storage for sixty-four data bits. Typically, the two register files each include eight registers, providing a total of sixteen registers to store the packed data sequences.
In order to move the packed data sequences to and from the extended register file, a new set of instructions is needed. Typically, to move the packed data sequences between the extended register file and the conventional integer register file, which provide a total of sixteen registers, four bits would be required to address a source operand and four more bits to address a destination operand. However, in the X86 Intel Architecture Series.TM., the decoder unit is designed to decode an instruction format that only provides three bits to address a source operand and three bits to address a destination operand. Therefore, encoding an instruction to transfer packed data between the 16 registers, using four bits to address each operand would require expensive modifications to the existing decoder unit provided in the Intel Architecture X86 Series.TM.. The modified decoder unit would also be more complex, most likely resulting in additional processing time to decode the instruction.
As such, what is desired is a set of instructions that are able to transfer packed data sequences to and from the extended integer register file, address up to 16 registers using only three bits to address a source operand and up to three bits to address a destination operand, and is encoded in an instruction format that is compatible with available decoder units.